Low-Power Reconfigurable Sensing Circuitry for the Internet-of-Things Paradigm

With ubiquitous wireless communication via Wi-Fi and nascent 5th Generation mobile communications, more devices -- both smart and traditionally dumb -- will be interconnected than ever before. This burgeoning trend is referred to as the Internet-of-Things. These new sensing opportunities place a larger burden on the underlying circuitry that must operate on finite battery power and/or within energy-constrained environments. New developments of low-power reconfigurable analog sensing platforms like field-programmable analog arrays (FPAAs) present an attractive sensing solution by processing data in the analog domain while staying flexible in design. This work addresses some of the contemporary challenges of low-power wireless sensing via traditional application-specific sensing and with FPAAs. A large emphasis is placed on furthering the development of FPAAs by making them more accessible to designers without a strong integrated-circuit background -- much like FPGAs have done for digital designers

A Recofigurable Tri-Band Interconnect for Future Network-On-Chip

The scaling of CMOS feature sizes has yielded the capability of integrating heterogeneous intellectual properties (IPs) like graphics processing units (GPUs), digital signal processors (DSPs) and central processing units (CPUs) on a single die. The collection of multiple IPs on a single die presents a problem of reliable communication due to congestion. The infrastructure that facilitates and manages communication among IPs is referred to as a network-on-chip (NoC). Its ultimate goal should be low latency with negligible power and area consumption. Unfortunately, as CMOS feature sizes have been scaling smaller, this has exacerbated latency and signal degradation due to increasing on-chip channel resistance. Furthermore, contemporary interfaces use baseband-only signaling and have critical limitations like exponential energy consumption, limited bandwidth and non-reconfigurable data access.;In this work, we propose an energy efficient tri-band (baseband + 2 RF bands) signaling interface that is capable of simultaneous bi-directional communication and reconfigurable data access. Additionally, communication is accomplished through a shared transmission line which reduces the overall number of global interconnections. As a result, this reduces area consumption and mitigates interconnection complexity. The primary signicance of this interconnect configuration compared to contemporary designs is an increase of bandwidth and energy efficiency.;The interconnect design is composed of a baseband transceiver and two RF (10Ghz and 20GHz) transceivers. The RF transceivers utilize amplitude-shift keying (ASK) modulation scheme. ASK modulation allows ease of circuit design, but most importantly it can be used for noncoherent communication, which we implemented in this system. Noncoherent ASK modulation is area conservative and power efficient since there is no longer a need for power-hungry frequency synthesizers. Moreover, noncoherent ASK demodulation accomplishes direct-down conversation through a passive self-mixer for additional power savings.;The results from our work show that a multi-band interconnect is a suitable remedy for future NoC communication that has been reaching its bandwidth limitation with baseband-only signaling. In conclusion, this work demonstrates a sustainable balance of energy efficiency and increased bandwidth for future on-chip interconnect designs

Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays

Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array

Does cardiac rehabilitation improve patient emotional well-being and illness perception

Background: Exercise-based cardiac rehabilitation (CR) programs promote lifestyle modification to improve prognosis in patients with cardiovascular disease. However, the effect of CR on patients’ perceived emotional well-being and illness perception has not been fully studied. Methods and Results: Two arms were used in this study. Arm 1 enrolled new CR participants and Arm 2 enrolled existing CR participants. Three validated questionnaires were employed. ANOVA and Wilcoxon signed rank test were used to compare differences between the groups. A total of 238 patients were enrolled from July 1 to December 31, 2015 with 131 patients (55%) in Arm 1 and 107 (45%) in Arm 2. Statistically significant differences of illness perception were seen between the groups. Arm 1 patients had statistically significant improvements in illness perception, perceived emotional support, and depression after CR. Conclusions: CR participation is associated with improved illness perception, perceived emotional support, and decreased depression